Comparative Simulation Study of InAs/Si and All-III-V Hetero Tunnel FETs

The Tunnel Field Effect Transistor (TFET) which utilizes the band-to-band-tunneling (BTBT) generation current of a gated pin-diode is regarded as promising candidate for ultra-low power circuits due to its potential sub-thermal slope which could enable a strongly reduced supply voltage (1). III-V/Si hetero junctions have been proposed for an improved on-current as compared to Si TFETs (2). Using small-gap semiconductors like InAs or In0.53Ga0.47As as source material increases the tunnel rate, while the wide band gap of the channel/drain materials Si or InP reduces ambipolar leakage. Nanowires (NWs) enable a good electrostatic control due to the surrounding gate and result in an efficient strain relaxation when the diameter is scaled down (3). Tomioka et al. and Björk et al. successfully integrated InAs NWs on Si by nanometer-scale hetero epitaxy based on selective area growth within patterned oxide films (4,5,6,7,8). Recently, Borg et al. demonstrated a new approach to integrate individual InAs/Si hetero-structure NW TFETs onto Si using selective epitaxy in nanotube templates. This approach allows to start with Si substrates of any crystalline orientation and to scale the diameter of the NWs down to reasonable limits (9). First p-type TFETs fabricated by this technology showed an overall performance with on-currents, Ion of 6 μA/μm (|VGS| = |VDS| = 1 V) and a roomtemperature subthreshold swing (SS) of ~160 mV/dec over at least three orders of magnitude in current (10). Temperature-dependent measurements indicated that the SS is limited by traps (10). The present simulation study is based on the geometry (see Figure 1), the measured IV-characteristics, and the limited electrical characterization of these devices.